Designing HPC silicon
at the frontier.

Owns the entire software stack from kernel-level drivers and runtime up through compiler back-ends and framework integration. Defines the developer experience that makes the silicon usable.

• Strategy: Roadmap for compiler, runtime, drivers, and high-level framework support (PyTorch, vLLM, TensorRT-class stacks).
• Performance: Drive operator-level optimisation, kernel scheduling, and end-to-end inference throughput.
• Hiring & org: Build and lead a software engineering organisation across compiler, runtime, and ML systems.
• Customer engagement: Partner with deployment customers on production-readiness and integration.

Top-tier executive role owning the entire digital design lifecycle from architecture to tape-out. Combines deep technical expertise in ASIC development with strategic leadership across high-performance AI silicon.

• Strategic leadership: Define the roadmap for RTL (SystemVerilog/Verilog) and verification methodologies (UVM, Formal).
• PPA optimisation: Drive low-power design, performance/area tuning, and architecture advancements (RISC-V, 3D-IC).
• First-pass silicon: Lead teams to rigorous verification — coverage-driven, assertions, VIP integration — to avoid costly redesigns.
• Cross-functional: Bridge architecture, physical design (STA/Synthesis), and software teams.

Lead the software engineering organisation across compiler, runtime, and inference-serving teams. Own execution quality, engineering process, hiring, and mentoring. Partner with the VP of Software Engineering on strategy and roadmap.

• Manage senior and principal ICs across compiler, runtime, kernels, and serving.
• Own delivery, quality, and tech-debt management across the software stack.
• Drive engineering process: code review, CI/CD, release management, on-call.
• Hire, develop, and retain senior software engineering talent.

Lead the architecture and performance modelling team. Own the chip's micro-architecture definition, the performance- projection methodology that backs every design decision, and the design-space exploration that picks where to spend area and power.

• Define and drive the micro-architecture across compute, memory hierarchy, and interconnect.
• Own the performance-modelling stack: cycle-accurate, analytical, and post-silicon correlation.
• Run design-space exploration; quantify PPA and workload-level impact of architecture choices.
• Mentor performance architects; partner with RTL, software, and product on roadmap.

Manage and grow the RTL design team. Responsible for the translation of micro-architecture specifications into synthesisable, verifiable, high-performance RTL.

• Lead block- and chip-level design reviews; enforce coding standards and design intent.
• Own micro-architecture/RTL trade-off decisions for PPA targets.
• Coordinate with DV, physical design, and architecture across the design schedule.
• Mentor senior and principal RTL engineers.

Build and lead the verification organisation. Set methodology, coverage strategy, and sign-off criteria across block, sub-system, and chip-level verification.

• Own the UVM testbench architecture, coverage closure, and regression strategy.
• Drive formal verification, assertion-based methodology, and VIP integration.
• Define sign-off criteria for block, integration, and chip-level milestones.
• Partner with emulation/post-silicon validation for full-cycle confidence.

Build the software stack that turns models into efficient workloads on our silicon. From kernels and runtime up through compiler back-ends and framework integration.

• Design compiler passes, kernel libraries, and runtime for inference workloads.
• Integrate with PyTorch, vLLM, and other production inference frameworks.
• Profile, tune, and optimise end-to-end model performance.
• Senior: 5+ years; Principal: 10+ years in ML systems / accelerator software.

Build the production inference serving layer that runs on top of our silicon. Continuous batching, request scheduling, KV-cache management, multi-tenant SLOs, and the vLLM/SGLang/TensorRT-LLM-class serving plumbing customers actually deploy.

• Design and implement the request scheduler, batcher, and KV-cache manager.
• Own latency-SLO and throughput targets across realistic LLM-serving workloads.
• Integrate with HTTP/gRPC front-ends, observability (metrics, tracing, request-level debug), and multi-tenant isolation.
• Senior: 5+ years; Principal: 10+ years in ML serving systems / distributed inference / production LLM stacks.

Bring up the on-chip CPU subsystem and own the low-level software that runs on it: bootloader, firmware, RTOS port, and the kernel-level drivers that talk to accelerator blocks.

• Bootloader, firmware, and RTOS bring-up on RISC-V / Arm CPU subsystems.
• Low-level drivers for accelerator, memory, and I/O blocks.
• Cache, MMU, interrupt, and power-management software.
• Senior: 5+ years; Principal: 10+ years of embedded / systems software.

Build and maintain the simulation infrastructure the hardware and software teams depend on: cycle-accurate models, virtual platforms, and the perf-modeling stack that mirrors silicon behaviour.

• Cycle-accurate and transaction-level models for compute, memory, and interconnect.
• Virtual platform / ISS integration for software bring-up before silicon.
• Calibration against RTL and post-silicon to keep the model honest.
• Senior: 5+ years; Principal: 10+ years of architecture / performance simulation.

Build the internal tooling that the chip-design team depends on: EDA flow automation, build systems, CI for RTL / DV / PD, and the developer experience that makes the hardware org fast.

• Automate synthesis, place & route, STA, and verification flows end-to-end.
• CI / regression infrastructure for RTL, DV, and physical design.
• Internal CLIs, dashboards, and dev-experience tooling for chip engineers.
• Senior: 5+ years; Principal: 10+ years of EDA tooling / hardware-eng infrastructure.

Define what good performance looks like and prove it before the RTL is written. Build the models that drive architecture decisions, identify bottlenecks, and validate silicon projections against silicon reality.

• Build cycle-accurate and analytical performance models for compute, memory hierarchy, and interconnect.
• Characterise target AI workloads; identify bottlenecks and quantify proposed architectural changes.
• Drive PPA trade-off studies; close the loop between architecture, RTL, and physical design.
• Senior: 5+ years; Principal: 10+ years of accelerator / CPU / GPU performance modelling.

Design and implement micro-architecture blocks for AI acceleration. Take ownership from spec to silicon-ready RTL.

• Author production-quality SystemVerilog/Verilog for compute, memory, and interconnect blocks.
• Optimise for power, area, and frequency under aggressive targets.
• Collaborate with verification, synthesis, and physical design.
• Senior: 5+ years; Principal: 10+ years of accelerator/SoC design.

Verify complex blocks and sub-systems. Build the testbench infrastructure that the rest of the team depends on.

• Architect UVM testbenches and write directed/random/coverage-driven tests.
• Drive coverage closure and root-cause failures end-to-end.
• Apply formal methods, assertions, and constrained-random where appropriate.
• Senior: 5+ years; Principal: 10+ years of pre-silicon DV.

Bring up the design on emulation/FPGA platforms for full-system validation, software bring-up, and customer demos before silicon returns.

• Partition the design for FPGA/emulation; manage memory models and clock domains.
• Build and maintain emulation infrastructure (Palladium, Veloce, Protium, or Xilinx/Altera FPGA boards).
• Co-validate hardware + software pre-silicon with the SW team.
• Senior: 5+ years; Principal: 10+ years of emulation/prototyping.

Own the chip's power architecture end-to-end: budget, low-power design intent, voltage / clock domains, and thermal envelope. Make sure the chip lands in its power and thermal targets.

• Top-down power budgeting across compute, memory, and I/O.
• Voltage / clock domain partitioning, DVFS, power gating, and UPF flows.
• Thermal modelling, package co-design, and silicon power characterisation.
• Senior: 5+ years; Principal: 10+ years of low-power / power architecture.

Design and integrate the chip's external memory subsystem. Own controller architecture, PHY integration, and end-to-end memory bandwidth and latency targets.

• DDR / LPDDR / HBM controller architecture and integration with vendor PHYs.
• Scheduler, refresh, and QoS design for mixed bandwidth- and latency-sensitive traffic.
• Bring-up, training, and post-silicon characterisation across PVT.
• Senior: 5+ years; Principal: 10+ years of memory-controller / DRAM subsystem design.

Design and integrate high-speed SerDes for chip-to-chip and chip-to-host interconnect. Own link bring-up, equalisation, and signal-integrity sign-off.

• SerDes architecture, PHY integration, and link training for multi-Gbps lanes.
• Equalisation, jitter budgeting, and channel modelling.
• Lab bring-up, BER characterisation, and post-silicon correlation.
• Senior: 5+ years; Principal: 10+ years of SerDes / high-speed I/O.

Own the PCIe / CXL host interface from controller IP integration through verification and post-silicon compliance.

• PCIe Gen4/Gen5/Gen6 controller integration; CXL where applicable.
• Link training, error handling, power management, and compliance.
• Driver-level co-debug with the software team.
• Senior: 5+ years; Principal: 10+ years of PCIe / host-interface design.

Own design-for-test across the chip: scan insertion, MBIST, ATPG pattern generation, and test-coverage closure for manufacturing test.

• Scan architecture, compression, and stitching across the design.
• MBIST insertion and repair flows for embedded memories.
• ATPG pattern generation and tester-time optimisation.
• Senior: 5+ years; Principal: 10+ years of DFT / manufacturing test.

Take RTL through synthesis, place & route, timing closure, and physical sign-off on advanced nodes. Own block- and chip-level PPA.

• Synthesis, floorplanning, place & route, and clock-tree synthesis.
• STA sign-off across PVT corners; ECO closure.
• Power, IR, EM, and physical-verification sign-off (DRC/LVS).
• Senior: 5+ years; Principal: 10+ years of physical design on advanced nodes.

Own the company's IT infrastructure end-to-end: server setup and operations, network, storage, identity, and endpoint management. Keep the company productive and secure.

• Set up and operate on-premise and cloud servers (compute, file, mail, web).
• Network: LAN/Wi-Fi, VPN, firewall, internet uplinks, monitoring.
• Storage and backups: NAS, snapshots, off-site archival.
• Endpoint & identity: laptop provisioning, MDM, SSO, access control, audit.

Support the executive team across calendar, travel, meetings, and operational logistics. Be the trusted point of contact that keeps the leadership running and the office functioning.

• Manage executive calendars, meetings, and travel across multiple time zones.
• Coordinate internal and external communications; prepare materials and follow-ups.
• Office and operational support: vendor coordination, expenses, on-site logistics.
• Handle sensitive information with discretion; partner closely with HR / Finance / Legal.